1. Field of the Invention
The present invention relates to a semiconductor device and method for fabricating the same, and more particularly, to a semiconductor device and method for fabricating the same which is adapted to prevent the latch-up of the semiconductor device.
2. Discussion of Related Art
CMOS circuits generally experience feedback which leads to a latch-up of the device and a temporary or permanent loss of the circuit functions. The latch-up resulting from such feedback and disadvantages following therefrom will be briefly described below.
FIG. 1 is a cross-sectional view of a general CMOS transistor, and FIG. 2 is an equivalent circuit diagram of the CMOS transistor shown in FIG. 1.
As illustrated in FIGS. 1 and 2, the CMOS transistor has a p-type well 11c formed in a defined region of an n-type substrate 11a. P.sup.+ -type impurity regions 11b, which are used as the emitter of a pnp-type transistor, are formed in the surface of the substrate 11a. Similarly, n.sup.+ -type impurity regions 11d used as the emitter of an npn-type transistor are formed in the surface of the substrate 11a corresponding to the p-type well 11c.
Consequently, the p.sup.+ -type impurity regions 11b, n-type substrate 11a and p-type well 11c form a pnp-type positive transistor in the horizontal direction, while the n.sup.+ -type impurity regions 11d, p-type well 11c and n-type substrate 11a form a npn-type positive transistor vertically. The bases of those two transistors provide positive feedback paths which are respectively driven by the collectors of different transistors.
Actually, a parasitic pnpn-junction is formed by the p- and n-junctions in providing both of the pnp- and npn-type transistors. Such a pnpn-junction is an unexpected result in the CMOS transistor and causes a deterioration in the characteristics of the device. That is, the pnpn-junction gives rise to a latch-up affecting the operation of the CMOS transistor.
As shown in FIGS. 1 and 2, a resistance R.sub.w is induced by series resistances in the p-type well 11c with respect to the current flowing into the p.sup.+ -type impurity regions 11b. Reference symbol R.sub.S indicates the resistance value of the substrate with respect to the n.sup.+ -type impurity regions 11d. The current flowing across the resistance R.sub.S can be calculated from the resistance value R.sub.S. The resistance value R.sub.S of the substrate may be obtained, but that of the p-type well 11c is hard to calculate due to non-uniform dopants and thickness of the depletion layer.
As described previously, the parasitic pnpn-junction has an influence upon the operation of the CMOS transistor and may be prevented by increasing the space between the devices. However, with increases in device integration, the space between the devices is reduced and the pnpn-junction is inevitable.
A method for fabricating a semiconductor device in accordance with prior art will be described in connection with FIGS. 3a-3e, which are cross-sectional views of the conventional semiconductor device at different stages during the fabrication process conventionally employed.
As shown in FIG. 3a, a silicon oxide layer 32 is formed via an oxidation of the surface of an n-type semiconductor substrate 31.
As shown in FIG. 3b, the silicon oxide layer 32 is eliminated in the region in which an n-channel transistor will be formed. A p-type impurity is then doped and diffused so as to form a p-type well region 33.
As shown in FIG. 3c, the silicon oxide layer 32 is selectively eliminated in the region in which the source and drain of a p-channel transistor will be formed on the surface of the n-type substrate 31. A p-type impurity is highly doped to form p.sup.+ -type impurity regions 34.
As shown in FIG. 3d, the silicon oxide layer 32 is selectively eliminated in order to form the source and drain of the n-channel transistor in the p-type well region 33. An n-type impurity is then doped and diffused, forming n.sup.+ -type impurity regions 35.
As shown in FIG. 3e, there are formed gate electrodes 36 and 36a of the n- and p-channel transistors, respectively, so that the semiconductor device of the prior art is completed.
Such a conventional fabrication of a semiconductor device however involves a disadvantage in that the resistance of the well R.sub.W cannot be reduced below a particular sheet resistance specified by the characteristics of the device in applying a substrate bias through the contact or the like after the completion of the fabrication.